Volume 5 Issue 3
Research Article | IJVSP-V5I3P101
Increasing Fault Coverage in Benchmark Circuit using Design for Testability and Test Pattern Generation using 6NCA
Shashank Srivastava and Tanusree Kaibartta
Research Article | IJVSP-V5I3P102
Multiplier Design Incorporating Logarithmic Number System for Residue Number System in Binary Logic
Shalini R.V and Dr.P.Sampath
Research Article | IJVSP-V5I3P103
Parametric Variations of Transistor Doping Profiles for Ultra Low Power Applications
Xhino M. Domi, Emadelden Fouad and Muhammad S. Ullah