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Research Article | Open Access
Volume 12 | Issue 5 | Year 2025 | Article Id. IJEEE-V12I5P107 | DOI : https://doi.org/10.14445/23488379/IJEEE-V12I5P107

Design and Analysis of 18nm finFET based 4-bit Shift Registers Using Transitional Hybrid Logic Flip-Flop

CH. Jaya Prakash, P HS Tejo Murthy, N. Mohana Vitaleswara Rao

Citation :

CH. Jaya Prakash, P HS Tejo Murthy, N. Mohana Vitaleswara Rao, "Design and Analysis of 18nm finFET based 4-bit Shift Registers Using Transitional Hybrid Logic Flip-Flop," International Journal of Electrical and Electronics Engineering, vol. 12, no. 5, pp. 69-76, 2025. Crossref, https://doi.org/10.14445/23488379/IJEEE-V12I5P107

Abstract

A shift register remains a kind of sequential logic circuitry primarily employed for the storage of digital data across many digital devices to enhance the functionality of digital circuits. The present paper presents an energy-effective shift register that employs a novel flip-flop involving an implicitly conditioned crossover architecture. The suggested flip-flop exhibits excellent reliability with minimal power usage. Employing four clocked devices in conjunction with the transitional condition approach further enhances the speed. In the simulations for the suggested architecture, the Serial In-Serial Out (SISO) and Parallel In-Parallel Out (PIPO) shift registers used the least amount of power. The architecture has just 16 devices and has been simulated using 18 nm finFET technology utilizing a 0.7 V power supply. The proposed flip-flop design employs hybrid logic transistors that reduce power consumption by at least 45% when compared to previous designs across various process corners. Also, the proposed flip-flop uses less power by atleast 15% across a wide supply voltage range of 0.7V to 1V, outperforming earlier devices in this respect. The suggested flip-flop is at least 20% quicker than current FFs across all process corners. The recommended 4-bit shift registers achieve the PVT criterion. It uses less power and operates slower at the Slow-Slow (SS) process corner and vice-versa at the Fast-Fast (FF) process corner. Furthermore, when the temperature rises, power utilization increases while delay decreases.

Keywords

PIPO, SISO, Flip-Flop, 18nm, finFET.

References

[1] Tse Nga Ng et al., “Scalable Printed Electronics: An Organic Decoder Addressing Ferroelectric Non-Volatile Memory,” Scientific Reports, vol. 2, no. 1, pp. 1-7, 2012.
[CrossRef] [Google Scholar] [Publisher Link]
[2] Hyun-Sik Kim et al., “A 10-Bit Column-Driver IC with Parasitic-Insensitive Iterative Charge-Sharing Based Capacitor-String Interpolation for Mobile Active-Matrix Lcds,” IEEE Journal of Solid-State Circuits, vol. 49, no. 3, pp. 766-782, 2014.
[CrossRef] [Google Scholar] [Publisher Link]
[3] Zushuai Xie, Zhiqiang Wu, and Jianhui Wu, “Low Voltage Delay Element with Dynamic Biasing Technique for Fully Integrated Cold-Start in Battery-Assistance DC Energy Harvesting Systems,” Applied Sciences, vol. 10, no. 19, pp. 1-13, 2020.
[CrossRef] [Google Scholar] [Publisher Link]
[4] Jin-Fa Lin et al., “Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 11, pp. 3033-3044, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[5] Piotr Otfinowski, and Pawel Grybos, “Low Area 4-Bit 5MS/S Flash-Type Digitizer for Hybrid-Pixel Detectors-Design Study in 180 Nm and 40 Nm CMOS,” Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, vol. 800, pp. 104-110, 2015.
[CrossRef] [Google Scholar] [Publisher Link]
[6] Natsumi Kawai et al., “A Fully Static Topologically-Compressed 21-Transistor Flip-Flop with 75% Power Saving,” IEEE Journal of Solid-State Circuits, vol. 49, no. 11, pp. 2526-2533, 2014.
[CrossRef] [Google Scholar] [Publisher Link]
[7] Gustavo A. Ruiz, and Mercedes Granda, “Efficient Low-Power Register Array with Transposed Access Mode,” Microelectronics Journal, vol. 45, no. 4, pp. 463-467, 2014.
[CrossRef] [Google Scholar] [Publisher Link]
[8] Vahid Jamshidi, and Mahdi Fazeli, “Design of Ultra-Low Power Current Mode Logic Gates Using Magnetic Cells,” AEU - International Journal of Electronics and Communications, vol. 83, pp. 270-279, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[9] T. D. Loveless et al., “Neutron-and Proton-Induced Single Event Upsets for D-and Dice-Flip/Flop Designs at a 40 Nm Technology Node,” IEEE Transactions on Nuclear Science, vol. 58, no. 3, pp. 1008-1014, 2011.
[CrossRef] [Google Scholar] [Publisher Link]
[10] Omid Sarbishei, and Mohammad Maymandi-Nejad, “A Novel Overlap-Based Logic Cell: An Efficient Implementation of Flip-Flops with Embedded Logic,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010, vol. 18, no. 2, pp. 222-231, 2010.
[CrossRef] [Google Scholar] [Publisher Link]
[11] Myint Wai Phyu et al., “Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 1, pp. 1-9, 2011.
[CrossRef] [Google Scholar] [Publisher Link]
[12] Jesus Blanco et al., “Ultra-Lightweight Algorithm for Generating Pseudo-Random Number Sequences in Passive UHF-RFID Tags,” Smart SysTech 2016; European Conference on Smart Objects, Systems and Technologies, Duisburg, Germany, pp. 1-5, 2016.
[Google Scholar] [Publisher Link]
[13] Jin-Fa Lin et al., “Low Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design,” Sensors, vol. 22, no. 15, pp. 1-16, 2022.
[CrossRef] [Google Scholar] [Publisher Link]
[14] Jun-Young Park et al., “Design of a Dual Change-Sensing 24T Flip-Flop in 65 nm CMOS Technology for Ultra Low-Power System Chips,” Electronics, vol. 11, no. 6, pp. 1-10, 2022.
[CrossRef] [Google Scholar] [Publisher Link]
[15] Chenyu Yin et al., “SEU Hardened D Flip-Flop Design with Low Area Overhead,” Micromachines, vol. 14, no. 10, pp. 1-12, 2023.
[CrossRef] [Google Scholar] [Publisher Link]
[16] Gicheol Shin et al., “An Ultra-Low-Power Fully-Static Contention-Free Flip-Flop with Complete Redundant Clock Transition and Transistor Elimination,” IEEE Journal of Solid-State Circuits, vol. 56, no. 10, pp. 3039-3048, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[17] Yongmin Lee, Gicheol Shin, and Yoonmyung Lee, “A Fully Static True-Single-Phase-Clocked Dual-Edge-Triggered Flip-Flop for Near-Threshold Voltage Operation in Iot Applications,” IEEE Access, vol. 8, pp. 40232–40245, 2020.
[CrossRef] [Google Scholar] [Publisher Link]
[18] Heng You et al., “A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS,” Electronics, vol. 9, no. 5, pp. 1-13, 2020.
[CrossRef] [Google Scholar] [Publisher Link]
[19] Syed Sadiq Vali, and N. Ashok kumar, “Design of Low Delay Low Power Hybrid Logic Based Flip-Flop Using Finfet,” e-Prime - Advances in Electrical Engineering, Electronics and Energy, vol. 9, 2024.
[CrossRef] [Google Scholar] [Publisher Link]
[20] Mohammad Torikul Islam Badal et al., “Low Power High-Efficiency Shift Register Using Implicit Pulse-Triggered Flip-Flop in 130 nm CMOS Process for Cryptographic RFID Tag,” Electronics, vol. 5, no. 4, pp. 1-13, 2016.
[CrossRef] [Google Scholar] [Publisher Link]
[21] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer Cmos Circuits,” Proceedings of the IEEE, vol. 91, no. 2, pp. 305-327, 2003.
[CrossRef] [Google Scholar] [Publisher Link]
[22] Debajit Bhattacharya, and Niraj K. Jha, “FinFETs: From Devices to Architectures,” Advances in Electronics, vol. 2014, pp. 1-21, 2014.
[CrossRef] [Google Scholar] [Publisher Link]
[23] M.V. Nageswara Rao et al., “Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications,” Journal of Electrical and Computer Engineering, vol. 2023, no. 1, pp. 1-13, 2023.
[CrossRef] [Google Scholar] [Publisher Link]
[24] Po-Yu Kuo et al., “A Novel Cross-Latch Shift Register Scheme for Low Power Applications,” Applied Sciences, vol. 11, no. 1, pp. 1-11, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[25] P. Syamala Devi, and G. Sasikala, “Design and Analysis of Low Power High Speed SBFF and MBFF for Signal Processing Applications,” e-Prime - Advances in Electrical Engineering, Electronics and Energy, vol. 7, 2024.
[CrossRef] [Google Scholar] [Publisher Link]