SSRG - IJVSP - Volume 6 Issue 3 - September - December 2019
Research Article | IJVSP-V6I3P101
Optimized Tsv Based 3d Integrated Circuit For Improve Power With Reduced Area Of Circuit
Aditya Sharma, Mr. Dinesh Chand Gupta
Research Article | IJVSP-V6I3P102
Modified radix 12 Multiplier for reducing area of designed circuit with reduce time delay
Akshay Sharma, Mr. Dinesh Chand Gupta
Research Article | IJVSP-V6I3P103
A Review on Low Power Memory Design Technique
Bhumika Chaurasia, Nishi Pandey, Meha Shrivastava
Research Article | IJVSP-V6I3P104
Comparison between the performance of the Simulated Annealing and Genetic Algorithms in Physical Conductor Orientation within FPGA
Roba khega, Kamal Mahmoud Afisa, Mohammed Yassin Subaih
Research Article | IJVSP-V6I3P105
Design of Programmable High Speed I/O S
Aruna Rao B P, Shanthi Prasad M J