SSRG - IJVSP - Volume 2 Issue 1 - January - April 2015
Research Article | IJVSP-V2I1P101
Design a Low Power Double Tail Comparator using Gated Clock and Power Gating Techniques
T.Loganayaki and R.Ramya
Research Article | IJVSP-V2I1P102
Architecture Design for an Adaptive Equalizer using LMS 2Tap filters
P.S. Radhika and N.Porutchelvam
Research Article | IJVSP-V2I1P103
High Performance and Low Power Asynchronous Data Sampling with Power Gated Double Edge Triggered Flip-Flop
R. Aruna and S.Thenappan
Research Article | IJVSP-V2I1P104
A Review on Area Efficient Parallel FIR Digital Filter Implementation
Arunadevi A . ,Chitra K. , GunaNandhini S. , Raghupathi T. , and Rejusha M
Research Article | IJVSP-V2I1P105
Design and Simulation of 4*1 Mux Based on Low Power Design Techniques
Ira Parashar,Preeti Sikarwar, Rashmi Singh, Soumya Chauhan and Mrs. Shivani Saxena