SSRG - IJECE - Volume 4 Issue 12 - December 2017
Research Article | IJECE-V4I12P101
Des IGN of Inexact Circuits using Gate-Level Pruning
Thilagavathy M. S and Dr. S. GopalaKrishnan
Research Article | IJECE-V4I12P102
Null Convention Logic (NCL) Design of Efficient Sorting Unit
E. Juhi Gladies and E. Thanga selvi
Research Article | IJECE-V4I12P103
Usage of Gain Cell Embedded Dram in Low Power Applications
P.Sujitha and M.Deivakani
Research Article | IJECE-V4I12P104
Data Pattern Aware Error Prevention Technique: Survey
M.Priyadharshini and T.Chelladurai